\doxysection{stm32h7xx\+\_\+hal\+\_\+tim\+\_\+ex.\+h}
\hypertarget{stm32h7xx__hal__tim__ex_8h_source}{}\label{stm32h7xx__hal__tim__ex_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_tim\_ex.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_tim\_ex.h}}
\mbox{\hyperlink{stm32h7xx__hal__tim__ex_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00047\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{00048\ \{}
\DoxyCodeLine{00049\ \ \ uint32\_t\ \mbox{\hyperlink{struct_t_i_m___hall_sensor___init_type_def_a08e8f098cb51159344135bab57d82d85}{IC1Polarity}};\ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{00075\ \}\ TIMEx\_BreakInputConfigTypeDef;}
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\DoxyCodeLine{00083\ \textcolor{comment}{/*\ Exported\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{00091\ \textcolor{preprocessor}{\#define\ TIM\_TIM1\_ETR\_GPIO\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00092\ \textcolor{preprocessor}{\#define\ TIM\_TIM1\_ETR\_COMP1\ \ \ \ \ \ \ TIM1\_AF1\_ETRSEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00093\ \textcolor{preprocessor}{\#define\ TIM\_TIM1\_ETR\_COMP2\ \ \ \ \ \ \ TIM1\_AF1\_ETRSEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00127\ \textcolor{preprocessor}{\#define\ TIM\_TIM23\_ETR\_GPIO\ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00131\ \textcolor{preprocessor}{\#define\ TIM\_TIM24\_ETR\_GPIO\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00145\ \textcolor{preprocessor}{\#define\ TIM\_BREAKINPUT\_BRK2\ \ \ \ 0x00000002U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00153\ \textcolor{preprocessor}{\#define\ TIM\_BREAKINPUTSOURCE\_BKIN\ \ \ \ \ 0x00000001U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00154\ \textcolor{preprocessor}{\#define\ TIM\_BREAKINPUTSOURCE\_COMP1\ \ \ \ 0x00000002U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00155\ \textcolor{preprocessor}{\#define\ TIM\_BREAKINPUTSOURCE\_COMP2\ \ \ \ 0x00000004U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00156\ \textcolor{preprocessor}{\#define\ TIM\_BREAKINPUTSOURCE\_DFSDM1\ \ \ 0x00000008U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00164\ \textcolor{preprocessor}{\#define\ TIM\_BREAKINPUTSOURCE\_DISABLE\ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00165\ \textcolor{preprocessor}{\#define\ TIM\_BREAKINPUTSOURCE\_ENABLE\ \ \ \ \ \ 0x00000001U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00183\ \textcolor{preprocessor}{\#define\ TIM\_TIM1\_TI1\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00186\ \textcolor{preprocessor}{\#define\ TIM\_TIM8\_TI1\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00189\ \textcolor{preprocessor}{\#define\ TIM\_TIM2\_TI4\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00190\ \textcolor{preprocessor}{\#define\ TIM\_TIM2\_TI4\_COMP1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI4SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00191\ \textcolor{preprocessor}{\#define\ TIM\_TIM2\_TI4\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI4SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00192\ \textcolor{preprocessor}{\#define\ TIM\_TIM2\_TI4\_COMP1\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI4SEL\_0\ |\ TIM\_TISEL\_TI4SEL\_1)\ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00194\ \textcolor{preprocessor}{\#define\ TIM\_TIM3\_TI1\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00195\ \textcolor{preprocessor}{\#define\ TIM\_TIM3\_TI1\_COMP1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00196\ \textcolor{preprocessor}{\#define\ TIM\_TIM3\_TI1\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00197\ \textcolor{preprocessor}{\#define\ TIM\_TIM3\_TI1\_COMP1\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_0\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00199\ \textcolor{preprocessor}{\#define\ TIM\_TIM5\_TI1\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00200\ \textcolor{preprocessor}{\#define\ TIM\_TIM5\_TI1\_CAN\_TMP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00201\ \textcolor{preprocessor}{\#define\ TIM\_TIM5\_TI1\_CAN\_RTP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00203\ \textcolor{preprocessor}{\#define\ TIM\_TIM12\_TI1\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00204\ \textcolor{preprocessor}{\#define\ TIM\_TIM12\_TI1\_SPDIF\_FS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00205\ }
\DoxyCodeLine{00206\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI1\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00207\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI1\_TIM2\_CH1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00208\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI1\_TIM3\_CH1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00209\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI1\_TIM4\_CH1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_0\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00210\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI1\_RCC\_LSE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_2)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00211\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI1\_RCC\_CSI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_2\ |\ TIM\_TISEL\_TI1SEL\_0)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00212\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI1\_RCC\_MCO2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_2\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00213\ }
\DoxyCodeLine{00214\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI2\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00215\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI2\_TIM2\_CH2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI2SEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00216\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI2\_TIM3\_CH2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI2SEL\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00217\ \textcolor{preprocessor}{\#define\ TIM\_TIM15\_TI2\_TIM4\_CH2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI2SEL\_0\ |\ TIM\_TISEL\_TI2SEL\_1)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00218\ }
\DoxyCodeLine{00219\ \textcolor{preprocessor}{\#define\ TIM\_TIM16\_TI1\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00220\ \textcolor{preprocessor}{\#define\ TIM\_TIM16\_TI1\_RCC\_LSI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00221\ \textcolor{preprocessor}{\#define\ TIM\_TIM16\_TI1\_RCC\_LSE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00222\ \textcolor{preprocessor}{\#define\ TIM\_TIM16\_TI1\_WKUP\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_0\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00223\ }
\DoxyCodeLine{00224\ \textcolor{preprocessor}{\#define\ TIM\_TIM17\_TI1\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00225\ \textcolor{preprocessor}{\#define\ TIM\_TIM17\_TI1\_SPDIF\_FS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00226\ \textcolor{preprocessor}{\#define\ TIM\_TIM17\_TI1\_RCC\_HSE1MHZ\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00227\ \textcolor{preprocessor}{\#define\ TIM\_TIM17\_TI1\_RCC\_MCO1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_0\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00228\ }
\DoxyCodeLine{00229\ \textcolor{preprocessor}{\#define\ TIM\_TIM23\_TI4\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00230\ \textcolor{preprocessor}{\#define\ TIM\_TIM23\_TI4\_COMP1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI4SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00231\ \textcolor{preprocessor}{\#define\ TIM\_TIM23\_TI4\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI4SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00232\ \textcolor{preprocessor}{\#define\ TIM\_TIM23\_TI4\_COMP1\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI4SEL\_0\ |\ TIM\_TISEL\_TI4SEL\_1)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00233\ }
\DoxyCodeLine{00234\ \textcolor{preprocessor}{\#define\ TIM\_TIM24\_TI1\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00235\ \textcolor{preprocessor}{\#define\ TIM\_TIM24\_TI1\_CAN\_TMP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00236\ \textcolor{preprocessor}{\#define\ TIM\_TIM24\_TI1\_CAN\_RTP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00237\ \textcolor{preprocessor}{\#define\ TIM\_TIM24\_TI1\_CAN\_SOC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI4SEL\_0\ |\ TIM\_TISEL\_TI4SEL\_1)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00241\ }
\DoxyCodeLine{00245\ \textcolor{comment}{/*\ End\ of\ exported\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00246\ }
\DoxyCodeLine{00247\ \textcolor{comment}{/*\ Exported\ macro\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00251\ }
\DoxyCodeLine{00255\ \textcolor{comment}{/*\ End\ of\ exported\ macro\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00256\ }
\DoxyCodeLine{00257\ \textcolor{comment}{/*\ Private\ macro\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00261\ \textcolor{preprocessor}{\#define\ IS\_TIM\_BREAKINPUT(\_\_BREAKINPUT\_\_)\ \ (((\_\_BREAKINPUT\_\_)\ ==\ TIM\_BREAKINPUT\_BRK)\ \ ||\ \(\backslash\)}}
\DoxyCodeLine{00262\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_BREAKINPUT\_\_)\ ==\ TIM\_BREAKINPUT\_BRK2))}}
\DoxyCodeLine{00263\ }
\DoxyCodeLine{00264\ \textcolor{preprocessor}{\#define\ IS\_TIM\_BREAKINPUTSOURCE(\_\_SOURCE\_\_)\ \ (((\_\_SOURCE\_\_)\ ==\ TIM\_BREAKINPUTSOURCE\_BKIN)\ \ ||\ \(\backslash\)}}
\DoxyCodeLine{00265\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_SOURCE\_\_)\ ==\ TIM\_BREAKINPUTSOURCE\_COMP1)\ ||\ \(\backslash\)}}
\DoxyCodeLine{00266\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_SOURCE\_\_)\ ==\ TIM\_BREAKINPUTSOURCE\_COMP2)\ ||\ \(\backslash\)}}
\DoxyCodeLine{00267\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_SOURCE\_\_)\ ==\ TIM\_BREAKINPUTSOURCE\_DFSDM1))}}
\DoxyCodeLine{00268\ }
\DoxyCodeLine{00269\ \textcolor{preprocessor}{\#define\ IS\_TIM\_BREAKINPUTSOURCE\_STATE(\_\_STATE\_\_)\ \ (((\_\_STATE\_\_)\ ==\ TIM\_BREAKINPUTSOURCE\_DISABLE)\ \ ||\ \(\backslash\)}}
\DoxyCodeLine{00270\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_STATE\_\_)\ ==\ TIM\_BREAKINPUTSOURCE\_ENABLE))}}
\DoxyCodeLine{00271\ }
\DoxyCodeLine{00272\ \textcolor{preprocessor}{\#define\ IS\_TIM\_BREAKINPUTSOURCE\_POLARITY(\_\_POLARITY\_\_)\ \ (((\_\_POLARITY\_\_)\ ==\ TIM\_BREAKINPUTSOURCE\_POLARITY\_LOW)\ \ ||\ \(\backslash\)}}
\DoxyCodeLine{00273\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_POLARITY\_\_)\ ==\ TIM\_BREAKINPUTSOURCE\_POLARITY\_HIGH))}}
\DoxyCodeLine{00274\ }
\DoxyCodeLine{00275\ \textcolor{preprocessor}{\#define\ IS\_TIM\_TISEL(\_\_TISEL\_\_)\ \ (((\_\_TISEL\_\_)\ ==\ TIM\_TIM1\_TI1\_GPIO)\ \ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00276\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM1\_TI1\_COMP1)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00277\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM8\_TI1\_GPIO)\ \ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00278\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM8\_TI1\_COMP2)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00279\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM2\_TI4\_GPIO)\ \ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00280\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM2\_TI4\_COMP1)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00281\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM2\_TI4\_COMP2)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00282\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM2\_TI4\_COMP1\_COMP2)\ \ ||\(\backslash\)}}
\DoxyCodeLine{00283\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM3\_TI1\_GPIO)\ \ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00284\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM3\_TI1\_COMP1)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00285\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM3\_TI1\_COMP2)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00286\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM3\_TI1\_COMP1\_COMP2)\ \ ||\(\backslash\)}}
\DoxyCodeLine{00287\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM5\_TI1\_GPIO)\ \ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00288\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM5\_TI1\_CAN\_TMP)\ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00289\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM5\_TI1\_CAN\_RTP)\ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00290\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM12\_TI1\_SPDIF\_FS)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00291\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM12\_TI1\_GPIO)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00292\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI1\_GPIO)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00293\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI1\_TIM2\_CH1)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00294\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI1\_TIM3\_CH1)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00295\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI1\_TIM4\_CH1)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00296\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI1\_RCC\_LSE)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00297\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI1\_RCC\_CSI)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00298\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI1\_RCC\_MCO2)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00299\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI2\_GPIO)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00300\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI2\_TIM2\_CH2)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00301\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI2\_TIM3\_CH2)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00302\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM15\_TI2\_TIM4\_CH2)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00303\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM16\_TI1\_GPIO)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00304\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM16\_TI1\_RCC\_LSI)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00305\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM16\_TI1\_RCC\_LSE)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00306\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM16\_TI1\_WKUP\_IT)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00307\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM17\_TI1\_GPIO)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00308\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM17\_TI1\_SPDIF\_FS)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00309\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM17\_TI1\_RCC\_HSE1MHZ)\ ||\(\backslash\)}}
\DoxyCodeLine{00310\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM17\_TI1\_RCC\_MCO1)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00311\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM23\_TI4\_GPIO)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00312\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM23\_TI4\_COMP1)\ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00313\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM23\_TI4\_COMP2)\ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00314\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM23\_TI4\_COMP1\_COMP2)\ ||\(\backslash\)}}
\DoxyCodeLine{00315\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM24\_TI1\_GPIO)\ \ \ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00316\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM24\_TI1\_CAN\_TMP)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00317\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM24\_TI1\_CAN\_RTP)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00318\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_TISEL\_\_)\ ==\ TIM\_TIM24\_TI1\_CAN\_SOC))}}
\DoxyCodeLine{00319\ }
\DoxyCodeLine{00320\ \textcolor{preprocessor}{\#define\ IS\_TIM\_REMAP(\_\_RREMAP\_\_)\ \ \ \ \ (((\_\_RREMAP\_\_)\ ==\ TIM\_TIM1\_ETR\_GPIO)\ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00321\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM1\_ETR\_ADC1\_AWD1)\ ||\(\backslash\)}}
\DoxyCodeLine{00322\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM1\_ETR\_ADC1\_AWD2)\ ||\(\backslash\)}}
\DoxyCodeLine{00323\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM1\_ETR\_ADC1\_AWD3)\ ||\(\backslash\)}}
\DoxyCodeLine{00324\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM1\_ETR\_ADC3\_AWD1)\ ||\(\backslash\)}}
\DoxyCodeLine{00325\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM1\_ETR\_ADC3\_AWD2)\ ||\(\backslash\)}}
\DoxyCodeLine{00326\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM1\_ETR\_ADC3\_AWD3)\ ||\(\backslash\)}}
\DoxyCodeLine{00327\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM1\_ETR\_COMP1)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00328\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM1\_ETR\_COMP2)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00329\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM8\_ETR\_GPIO)\ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00330\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM8\_ETR\_ADC2\_AWD1)\ ||\(\backslash\)}}
\DoxyCodeLine{00331\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM8\_ETR\_ADC2\_AWD2)\ ||\(\backslash\)}}
\DoxyCodeLine{00332\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM8\_ETR\_ADC2\_AWD3)\ ||\(\backslash\)}}
\DoxyCodeLine{00333\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM8\_ETR\_ADC3\_AWD1)\ ||\(\backslash\)}}
\DoxyCodeLine{00334\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM8\_ETR\_ADC3\_AWD2)\ ||\(\backslash\)}}
\DoxyCodeLine{00335\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM8\_ETR\_ADC3\_AWD3)\ ||\(\backslash\)}}
\DoxyCodeLine{00336\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM8\_ETR\_COMP1)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00337\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM8\_ETR\_COMP2)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00338\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM2\_ETR\_GPIO)\ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00339\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM2\_ETR\_COMP1)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00340\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM2\_ETR\_COMP2)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00341\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM2\_ETR\_RCC\_LSE)\ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00342\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM2\_ETR\_SAI1\_FSA)\ \ ||\(\backslash\)}}
\DoxyCodeLine{00343\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM2\_ETR\_SAI1\_FSB)\ \ ||\(\backslash\)}}
\DoxyCodeLine{00344\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM3\_ETR\_GPIO)\ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00345\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM3\_ETR\_COMP1)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00346\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM5\_ETR\_GPIO)\ \ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00347\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM5\_ETR\_SAI2\_FSA)\ \ ||\(\backslash\)}}
\DoxyCodeLine{00348\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM5\_ETR\_SAI2\_FSB)\ \ ||\(\backslash\)}}
\DoxyCodeLine{00349\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM23\_ETR\_GPIO)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00350\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM23\_ETR\_COMP1)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00351\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM23\_ETR\_COMP2)\ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00352\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM24\_ETR\_GPIO)\ \ \ \ \ ||\(\backslash\)}}
\DoxyCodeLine{00353\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM24\_ETR\_SAI4\_FSA)\ ||\(\backslash\)}}
\DoxyCodeLine{00354\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM24\_ETR\_SAI4\_FSB)\ ||\(\backslash\)}}
\DoxyCodeLine{00355\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM24\_ETR\_SAI1\_FSA)\ ||\(\backslash\)}}
\DoxyCodeLine{00356\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_RREMAP\_\_)\ ==\ TIM\_TIM24\_ETR\_SAI1\_FSB))}}
\DoxyCodeLine{00357\ }
\DoxyCodeLine{00361\ \textcolor{comment}{/*\ End\ of\ private\ macro\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00362\ }
\DoxyCodeLine{00363\ \textcolor{comment}{/*\ Exported\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00367\ }
\DoxyCodeLine{00372\ \textcolor{comment}{/*\ \ Timer\ Hall\ Sensor\ functions\ \ **********************************************/}}
\DoxyCodeLine{00373\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_HallSensor\_Init(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ \textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___hall_sensor___init_type_def}{TIM\_HallSensor\_InitTypeDef}}\ *sConfig);}
\DoxyCodeLine{00374\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_HallSensor\_DeInit(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00375\ }
\DoxyCodeLine{00376\ \textcolor{keywordtype}{void}\ HAL\_TIMEx\_HallSensor\_MspInit(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00377\ \textcolor{keywordtype}{void}\ HAL\_TIMEx\_HallSensor\_MspDeInit(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00378\ }
\DoxyCodeLine{00379\ \textcolor{comment}{/*\ Blocking\ mode:\ Polling\ */}}
\DoxyCodeLine{00380\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_HallSensor\_Start(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00381\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_HallSensor\_Stop(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00382\ \textcolor{comment}{/*\ Non-\/Blocking\ mode:\ Interrupt\ */}}
\DoxyCodeLine{00383\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_HallSensor\_Start\_IT(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00384\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_HallSensor\_Stop\_IT(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00385\ \textcolor{comment}{/*\ Non-\/Blocking\ mode:\ DMA\ */}}
\DoxyCodeLine{00386\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_HallSensor\_Start\_DMA(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ *pData,\ uint16\_t\ Length);}
\DoxyCodeLine{00387\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_HallSensor\_Stop\_DMA(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00391\ }
\DoxyCodeLine{00396\ \textcolor{comment}{/*\ \ Timer\ Complementary\ Output\ Compare\ functions\ \ *****************************/}}
\DoxyCodeLine{00397\ \textcolor{comment}{/*\ Blocking\ mode:\ Polling\ */}}
\DoxyCodeLine{00398\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OCN\_Start(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00399\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OCN\_Stop(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00400\ }
\DoxyCodeLine{00401\ \textcolor{comment}{/*\ Non-\/Blocking\ mode:\ Interrupt\ */}}
\DoxyCodeLine{00402\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OCN\_Start\_IT(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00403\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OCN\_Stop\_IT(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00404\ }
\DoxyCodeLine{00405\ \textcolor{comment}{/*\ Non-\/Blocking\ mode:\ DMA\ */}}
\DoxyCodeLine{00406\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OCN\_Start\_DMA(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel,\ \textcolor{keyword}{const}\ uint32\_t\ *pData,}
\DoxyCodeLine{00407\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint16\_t\ Length);}
\DoxyCodeLine{00408\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OCN\_Stop\_DMA(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00412\ }
\DoxyCodeLine{00417\ \textcolor{comment}{/*\ \ Timer\ Complementary\ PWM\ functions\ \ ****************************************/}}
\DoxyCodeLine{00418\ \textcolor{comment}{/*\ Blocking\ mode:\ Polling\ */}}
\DoxyCodeLine{00419\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_PWMN\_Start(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00420\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_PWMN\_Stop(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00421\ }
\DoxyCodeLine{00422\ \textcolor{comment}{/*\ Non-\/Blocking\ mode:\ Interrupt\ */}}
\DoxyCodeLine{00423\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_PWMN\_Start\_IT(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00424\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_PWMN\_Stop\_IT(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00425\ \textcolor{comment}{/*\ Non-\/Blocking\ mode:\ DMA\ */}}
\DoxyCodeLine{00426\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_PWMN\_Start\_DMA(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel,\ \textcolor{keyword}{const}\ uint32\_t\ *pData,}
\DoxyCodeLine{00427\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint16\_t\ Length);}
\DoxyCodeLine{00428\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_PWMN\_Stop\_DMA(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channel);}
\DoxyCodeLine{00432\ }
\DoxyCodeLine{00437\ \textcolor{comment}{/*\ \ Timer\ Complementary\ One\ Pulse\ functions\ \ **********************************/}}
\DoxyCodeLine{00438\ \textcolor{comment}{/*\ Blocking\ mode:\ Polling\ */}}
\DoxyCodeLine{00439\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OnePulseN\_Start(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ OutputChannel);}
\DoxyCodeLine{00440\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OnePulseN\_Stop(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ OutputChannel);}
\DoxyCodeLine{00441\ }
\DoxyCodeLine{00442\ \textcolor{comment}{/*\ Non-\/Blocking\ mode:\ Interrupt\ */}}
\DoxyCodeLine{00443\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OnePulseN\_Start\_IT(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ OutputChannel);}
\DoxyCodeLine{00444\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_OnePulseN\_Stop\_IT(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ OutputChannel);}
\DoxyCodeLine{00448\ }
\DoxyCodeLine{00453\ \textcolor{comment}{/*\ Extended\ Control\ functions\ \ ************************************************/}}
\DoxyCodeLine{00454\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_ConfigCommutEvent(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ \ InputTrigger,}
\DoxyCodeLine{00455\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint32\_t\ \ CommutationSource);}
\DoxyCodeLine{00456\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_ConfigCommutEvent\_IT(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ \ InputTrigger,}
\DoxyCodeLine{00457\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint32\_t\ \ CommutationSource);}
\DoxyCodeLine{00458\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_ConfigCommutEvent\_DMA(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ \ InputTrigger,}
\DoxyCodeLine{00459\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint32\_t\ \ CommutationSource);}
\DoxyCodeLine{00460\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_MasterConfigSynchronization(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,}
\DoxyCodeLine{00461\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___master_config_type_def}{TIM\_MasterConfigTypeDef}}\ *sMasterConfig);}
\DoxyCodeLine{00462\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_ConfigBreakDeadTime(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,}
\DoxyCodeLine{00463\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___break_dead_time_config_type_def}{TIM\_BreakDeadTimeConfigTypeDef}}\ *sBreakDeadTimeConfig);}
\DoxyCodeLine{00464\ \textcolor{preprocessor}{\#if\ defined(TIM\_BREAK\_INPUT\_SUPPORT)}}
\DoxyCodeLine{00465\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_ConfigBreakInput(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ BreakInput,}
\DoxyCodeLine{00466\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{keyword}{const}\ TIMEx\_BreakInputConfigTypeDef\ *sBreakInputConfig);}
\DoxyCodeLine{00467\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM\_BREAK\_INPUT\_SUPPORT\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00468\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_GroupChannel5(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Channels);}
\DoxyCodeLine{00469\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_RemapConfig(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ Remap);}
\DoxyCodeLine{00470\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ \ HAL\_TIMEx\_TISelection(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ TISelection,\ uint32\_t\ Channel);}
\DoxyCodeLine{00471\ \textcolor{preprocessor}{\#if\ defined(TIM\_BDTR\_BKBID)}}
\DoxyCodeLine{00472\ }
\DoxyCodeLine{00473\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_DisarmBreakInput(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ BreakInput);}
\DoxyCodeLine{00474\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_TIMEx\_ReArmBreakInput(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ uint32\_t\ BreakInput);}
\DoxyCodeLine{00475\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM\_BDTR\_BKBID\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00479\ }
\DoxyCodeLine{00484\ \textcolor{comment}{/*\ Extended\ Callback\ **********************************************************/}}
\DoxyCodeLine{00485\ \textcolor{keywordtype}{void}\ HAL\_TIMEx\_CommutCallback(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00486\ \textcolor{keywordtype}{void}\ HAL\_TIMEx\_CommutHalfCpltCallback(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00487\ \textcolor{keywordtype}{void}\ HAL\_TIMEx\_BreakCallback(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00488\ \textcolor{keywordtype}{void}\ HAL\_TIMEx\_Break2Callback(\mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00492\ }
\DoxyCodeLine{00497\ \textcolor{comment}{/*\ Extended\ Peripheral\ State\ functions\ \ ***************************************/}}
\DoxyCodeLine{00498\ \mbox{\hyperlink{group___t_i_m___exported___types_gae0994cf5970e56ca4903e9151f40010c}{HAL\_TIM\_StateTypeDef}}\ HAL\_TIMEx\_HallSensor\_GetState(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim);}
\DoxyCodeLine{00499\ \mbox{\hyperlink{group___t_i_m___exported___types_ga1a70fcbe9952e18af5c890e216a15f34}{HAL\_TIM\_ChannelStateTypeDef}}\ HAL\_TIMEx\_GetChannelNState(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___handle_type_def}{TIM\_HandleTypeDef}}\ *htim,\ \ uint32\_t\ ChannelN);}
\DoxyCodeLine{00503\ }
\DoxyCodeLine{00507\ \textcolor{comment}{/*\ End\ of\ exported\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00508\ }
\DoxyCodeLine{00509\ \textcolor{comment}{/*\ Private\ functions-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00513\ \textcolor{keywordtype}{void}\ TIMEx\_DMACommutationCplt(\mbox{\hyperlink{group___d_m_a___exported___types_ga41b754a906b86bce54dc79938970138b}{DMA\_HandleTypeDef}}\ *hdma);}
\DoxyCodeLine{00514\ \textcolor{keywordtype}{void}\ TIMEx\_DMACommutationHalfCplt(\mbox{\hyperlink{group___d_m_a___exported___types_ga41b754a906b86bce54dc79938970138b}{DMA\_HandleTypeDef}}\ *hdma);}
\DoxyCodeLine{00518\ \textcolor{comment}{/*\ End\ of\ private\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00519\ }
\DoxyCodeLine{00523\ }
\DoxyCodeLine{00527\ }
\DoxyCodeLine{00528\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00529\ \}}
\DoxyCodeLine{00530\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00531\ }
\DoxyCodeLine{00532\ }
\DoxyCodeLine{00533\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H7xx\_HAL\_TIM\_EX\_H\ */}\textcolor{preprocessor}{}}

\end{DoxyCode}
